1. Field of the Invention
The present invention relates to a method and a device for driving an AC type plasma display panel.
A plasma display panel (PDP) has been widely used as a monitor of a television or a computer since a color screen was commercialized. As a using environment is diversified along with the widespread use, a driving method is desired that can realize a stable display without being affected by temperature variation or voltage regulation of a power source.
2. Description of the Prior Art
As a color display device, a surface discharge format AC type PDP is commercialized. The surface discharge format means a structure in which display electrodes (first electrodes and second electrodes) to be anodes and cathodes in display discharge for ensuring luminance are arranged on a front or a back substrate in parallel, and address electrodes (third electrodes) are arranged so as to cross the display electrode pairs. There are two arrangement forms of the display electrodes. In the first form, a pair of display electrodes is arranged for each row of a matrix display. In the second form, the first and the second display electrodes are arranged alternately at a constant pitch. In the second form, the display electrode except both ends of the arrangement works for displays of two rows. Regardless of an arrangement form, the display electrode pairs are covered with a dielectric layer.
In a display of a surface discharge format PDP, one of the display electrode pair (the second electrode) corresponding to a row is used as a scan electrode for selecting a row, so that address discharge is generated between a scan electrode and an address electrode, which causes address discharge between display electrodes. Thus, an addressing is performed controlling wall charge quantity in the dielectric layer in accordance with display contents. After the addressing, sustaining voltage Vs having alternating polarities is applied to the display electrode pair. The sustaining voltage Vs satisfies the following inequality (1).
VfXYxe2x88x92VwXY less than Vs less than VfXYxe2x80x83xe2x80x83(1)
Here, VfXY denotes discharge start voltage between display electrodes, and VwXY denotes wall voltage between display electrodes.
By applying the sustaining voltage Vs, cell voltage (the sum of drive voltage that is applied to the electrode and the wall voltage) exceeds the discharge start voltage VfXY only in cells having predetermined quantity of wall charge so that surface discharge is generated on the surface of the substrate. When the application period is shortened, light emission looks as being continuous.
A discharge cell of a PDP is basically a binary light emission element. Accordingly, a halftone is reproduced by setting integral light emission quantity of an individual discharge cell in a frame period in accordance with a gradation value of input image data. A color display is a type of the gradation display, and the display color is determined by combining luminance values of three primary colors. For the gradation display, a method is used in which one frame is made of plural subframes (subfields in the case of an interlace display) having luminance weights, and the integral light emission quantity is set by combining on and off of the light emission for each subframe.
FIG. 12 is a diagram of voltage waveforms showing a general driving sequence. In FIG. 12, reference letters X, Y and A denote the first display electrode, the second display electrode and the address electrode, respectively. Each of the numeric letters 1xe2x88x92n added to X and Y indicates the arrangement order of the row corresponding to the display electrodes X and Y. Each of the numeric letters 1xe2x88x92m added to A indicates the arrangement order of the column corresponding to the address electrode A.
A subframe period Tsf assigned to a subframe includes a reset period TR for equalizing charge distribution in the screen, an address period TA for forming the charge distribution in accordance with display contents by applying a scan pulse Py and an address pulse Pa and a sustain period (also referred to as a display period) TS for ensuring a luminance value corresponding to a gradation value by applying a display pulse Ps. The lengths of the reset period TR and the address period TA are constant regardless of a luminance weight, while the length of the sustain period TS is longer as the luminance weight is larger. The illustrated set of waveforms is an example. It is possible to modify the amplitude, the polarity and the timing variously.
In the reset period TR, a writing pulse Prx is applied to all the display electrodes X so that whole surface discharge is generated and the wall charge is erased by self-erasing discharge accompanied with the end of the pulse application. The address electrode A is supplied with a pulse Pra for preventing undesired discharge. There is a method for equalizing the charge distribution, in which a ramp waveform pulse is applied so as to control the charge quantity. In the address period TA, all the display electrodes Y are biased to non-selection potential Vya2 at the start point in time, and then the display electrodes Y corresponding to the selected row i (1xe2x89xa6ixe2x89xa6n) are biased to selection potential Vya1 temporarily (application of the scan pulse). In synchronization with the row selection, the address electrodes A are biased to the selection potential Vaa only in the column including the selected cells generating the address discharge of the selected rows (application of the address pulse). The address electrodes A of the column including the non-selected cells are biased to the ground potential (usually zero volts). The display electrodes X are biased to a constant potential Vxa from the start to the end of the addressing regardless of being the selected row or the non-selected row. In the sustain period TS, the display pulse Ps having the amplitude Vs is applied to the display electrode Y and the display electrode X alternately. The number of the pulse application is substantially proportional to the luminance weight.
In a PDP, internal electrification characteristics depend on operating temperature, so that a difference of the charged state can be generated between cells depending on a display pattern. As a result, the conventional driving method has a problem that an addressing error is apt to occur because of excessive or insufficient charge at interelectrode AY between the address electrode A and the display electrode Y. This problem will be explained as follows.
FIG. 13 is a diagram of waveforms showing cell voltage variation in the address period of the conventional method. In FIG. 13, thick solid lines indicate appropriate variation of the cell voltage (the sum of the applied voltage and the wall voltage), while chain lines indicate inappropriate variation of the cell voltage.
Here, the k-th cell in the selection order j-th row is noted. A display pattern is supposed, in which an address electrode A corresponding to the k-th column is biased to the address potential Vaa, i.e., the display data D1,k-Di,k of the k-th column and of the first through i-th rows are the selected data in the period before the noted row becomes the selected row and while the first through i-th (i less than j) rows are the selected rows. The wall voltage at the interelectrode XY at the start point of the address period TA is denoted by Vwxy1, and wall voltage at the interelectrode AY at the start point of the address period TA is denoted by Vway1.
If the operating temperature is relatively low, the wall voltage does not alter before the noted row becomes the selected row remaining substantially at the initial value. Therefore, when the noted row becomes the selected row, and the display electrode Yj is biased to the selection potential Vya1, and when the address electrode Ak is biased to the address potential Vaa, the cell voltage (Vway1+Vaaxe2x88x92Vya1) at the interelectrode AY exceeds a discharge threshold level VfAY, so that address discharge is generated. The address discharge causes changes of the wall voltage at the interelectrode AY and the wall voltage at the interelectrode XY, followed by formation of a charged state that is suitable for an operation of the subsequent sustain period. The address discharge causes wall voltage Vwxy2 at the interelectrode XY and wall voltage Vway2 at the interelectrode AY.
Before the noted row becomes the selected row, even if the address electrode Ak is biased to the address potential Vaa, discharge cannot be generated because the cell voltage at the interelectrode AY of the noted row is lower than the discharge start threshold level VfAY. However, when environment temperature rises, or heat due to the display is accumulated, the cell temperature may rise above the normal temperature. Accordingly, the cell voltage at the interelectrode AY approaches to the discharge start threshold level VfAY, and the wall voltage at the interelectrode AY may alter when microdischarge is generated even if the cell voltage is below VfAY. There is also the case where remaining minute quantity of space charge affects the wall voltage to alter. Due to the variation of the wall voltage, the cell voltage at the interelectrode AY when the noted row becomes the selected row becomes lower than the normal voltage, and the address discharge intensity (variation quantity of the wall voltage due to the discharge) is lowered. Therefore, the variation quantity of the wall voltage at the interelectrode XY, which is expected to occur at the same time as the variation of the wall voltage at the interelectrode AY during the address discharge, also becomes little. In this case, since the wall voltage (Vwxy2xe2x80x2) at the interelectrode XY of the cell to be lighted is insufficient, a lighting error may occur in the subsequent sustain period, resulting in a disturbance of the display.
In order to suppress this undesired variation of the wall voltage, it is good to decrease the difference between the non-selection potential Vya2 of the display electrode Y and the address potential Vaa of the address electrode A. However, the difference between the selection potential Vya1 and the address potential Vaa should be set to a sufficiently large value for ensuring intensity of the address discharge at the interelectrode AY. Therefore, decrease of the difference between the non-selection potential Vya2 and the address potential Vaa and the drop in the address potential Vaa close to the address potential of the non-selection potential mean that the difference between the selection potential Vya1 and the non-selection potential Vya2 of the display electrode Y is enlarged and require increase of withstand voltage of scan circuit components. In the address period, voltage corresponding to the difference between the selection potential Vya1 and the non-selection potential Vya2 is applied across the power source terminals of integrated circuit components called scan drivers. It is necessary to use scan drivers having specifications that can satisfy the voltage. The increase of the withstand voltage of the integrated circuit will cause a substantial increase of the component price.
An object of the present invention is to stabilize a display by realizing the addressing that is hardly affected by operating environment without increasing withstand voltage of circuit components.
In the present invention, a drive halt period in which no pulse is applied and no electrode bias is switched is provided purposely between at least one of the plural subframe periods and the subsequent subframe period. The language xe2x80x9cpurposelyxe2x80x9d means that the length of the drive halt period is longer than 100 microns, preferably more than 200 microns, and is sufficiently long compared with a pulse interval of micron order that is usually set. The form in which a part of the frame period is made the drive halt period includes a light emission control in which at least one subframe is forced to be a non-lighted subframe. In the subframe to be the non-lighted subframe, display discharge is not generated, so at least the sustain period becomes substantially the drive halt period. Furthermore, in the case of a write address format in which the wall voltage of the cell to be lighted is raised, the address period also becomes substantially the drive halt period. By providing the drive halt period, the disturbance of display can be reduced because of the following reason.
It is confirmed by experiments that the disturbance of display due to the incorrect addressing appears conspicuously under the following conditions (1)-(3).
(1) when the surface of the panel is exposed to high temperature.
(2) when a display load factor is 100% or nearly 100%.
(3) when the display load factor of one of the red, green and blue colors is 100% or nearly 100% in a color display.
Here, xe2x80x9cdisplay load factorxe2x80x9d means a value depending on the sum of the gradation values in one screen of the image data to be displayed and is defined as an average value of a ratio Di/Dmax of all cells when Di (0xe2x89xa6Dixe2x89xa6Dmax) is the gradation value of the cell i in one frame.
In addition, the following facts (4)-(6) are proved by experiments.
(4) A lighting error is apt to occur in a subframe subsequent to the subframe having a large luminance weight.
(5) A lighting error is generated uniformly in any subframe regardless of the luminance weight.
(6) The larger the luminance weight of the subframe in which a lighting error occurs, the more the lighting error affects the image quality as display unevenness.
Concerning the fact (4), there is a relationship that if a luminance weight of a certain subframe is large (i.e., if the number of display pulses is large), a wall voltage variation Vway of the interelectrode AY in the address period of the subsequent subfield increases. A concrete example of this relationship is shown in FIG. 1.
Considering the conditions and facts (1)-(6), a solution of the problem has been searched. Then, the following facts (7) and (8) are discovered.
(7) A drive halt period is provided between the end of a display of a subframe in which cells are lighted and the start of the addressing of the subsequent subframe. When increasing the length of the drive halt period (i.e., the interval time), the wall voltage variation Vway of the interelectrode AY in the next subframe decreases, and the lighting error hardly occurs.
(8) If a subframe subsequent to the subframe in which cells are lighted is the non-lighted subframe, the lighting error hardly occurs in the further subsequent subframe, so that the same effect can be obtained as the above-mentioned method in which the interval time is elongated. A concrete example of the relationship between the interval time and the wall voltage variation Vway is shown in FIG. 2. In this example, the wall voltage variation Vway can be reduced to below 10 volts when the interval time is 500 microns, and can be reduced down to approximately one volt when the interval time is 1000 microns.
As explained above, it is effective in stabilizing a display to provide the drive halt period. However, since a frame period of a full motion display is fixed to approximately 16.7 milliseconds, the time that can be allocated to the subframe is reduced when a part of the frame period is allocated to the drive halt period. If the number of display pulses is reduced, the luminance is lowered. If the number of subframes is reduced, gradation quality is deteriorated. Therefore, it is practical to provide the drive halt period only when the lighting error is apt to occur, i.e., when a display load is large. In general, when the display load is large, the temperature of the panel surface is high.
When driving a PDP, an automatic power control (APC) is usually performed in which the number of display pulses is decreased responding to increase of the display load for reducing power consumption. When the APC is performed, the sustain period is shortened for a large display load. Therefore, the sum of the subframe periods becomes shorter than the frame period, so that a free time corresponding to the difference between the sum of the subframe periods and the frame period is generated.
The free time generated by the APC is divided to be distributed within the frame period, so that the lighting error can be reduced effectively. If the above-mentioned fact (4) is noted, it is desirable to provide the drive halt period immediately after a subframe having a large luminance weight. If the above-mentioned fact (6) is noted, it is desirable to provide the drive halt period immediately before a subframe having a large luminance weight. In either case, an optimal length of the interval time is determined by the relationship of the luminance weights of the subframes before and after the drive halt period. Therefore, if there is a free time longer than the optimal length, it is desirable to allocate the free time to plural drive halt periods without making one drive halt period longer than a necessary length.